1. Technical Field
The present invention generally relates to a semiconductor memory system, and more particularly, to a test circuit of a semiconductor memory system.
2. Related Art
According to the recent semiconductor integrated circuit technology, a memory and a processor may be integrated into one chip, thereby reducing noise and uncertainty which may occur between the memory and the processor during signal transmission. The technology for integrating heterogeneous electronic circuit blocks into a single chip may include SoC (System on Chip) or SiP (System in Package). The SoC or SiP may effectively reduce a chip area and realize a high integration degree, and the market thereof is being gradually expanded.
FIG. 1 is a configuration diagram of a conventional semiconductor memory system in which a memory and a processor are integrated.
The semiconductor memory system includes a processor 10 and a stacked memory 20 which are mounted over a substrate 40 including a plurality of external connection terminals 41. At this time, the semiconductor memory system may further include an interposer 30 to connect the substrate 40 to the processor 10 and the stacked memory 20. The processor 10 and stacked memory 20 may also comprise input/output sections (I/O) for communications.
Referring to FIG. 1, there is no connection path through which a memory can be individually accessed from outside, after the semiconductor memory system is packaged. Therefore, it is impossible to perform a probe test using the existing equipment. Accordingly, a test method has been adopted, in which a test circuit is inserted into the semiconductor memory system and a test result obtained by the test circuit is checked through a test pin of the substrate 40.
FIG. 2 is a block diagram of a conventional boundary scan test circuit.
The boundary scan test circuit is a test circuit which to verify a signal input path between a processor and a memory inside a semiconductor memory system, and may be inserted into the memory, for example.
The boundary scan test circuit illustrated in FIG. 2 includes a latch unit 21 and a transmission unit 22.
The latch unit 21 includes a plurality of latches LAT1 to LATn, and the transmission unit 22 includes a plurality of flip-flops F/F1 to F/Fn connected between the respective latches LAT1 to LATn and configured to operate in synchronization with a test clock SCLK. The latches LAT1 to LATn are configured to output one signal among input signals received through input pins I/O—0, I/O—1, . . . , I/O_n and output signals of the respective flip-flops F/F1 to F/Fn connected thereto, in response to a control signal SSH. The control signal SSH is a signal for selectively outputting the input signals of the latch unit 21. Logic0 is an initial setting signal. The latch unit 21 outputs the Logic0 and the output signals of the flip-flops F/F1 to F/Fn when the control signal SSH is activated, and outputs the input signals received through the respective input pins I/O—0, I/O—1, . . . , I/O_n when the control signal SSH is deactivated.
FIG. 3 is a waveform diagram illustrating a test operation of the boundary scan test circuit.
When the control signal SSH is deactivated at a low level, the latch unit 21 transmits the input signals received through the input pins I/O—0, I/O—1, . . . , I/O_n to the transmission unit 22. Therefore, the flip-flops F/F1 to F/Fn receive the input signals received through the respective input pins I/O—0, I/O—1, . . . , I/O_n. Then, when the control signal SSH is activated at a high level, the latch unit 21 transmits the output signals of the flip flips F/F1 to F/FN to the transmission unit 22. Furthermore, when the test clock signal SCLK is enabled, the respective flip-flops F/F1 to F/Fn store and output the received data in synchronization with the test clock signal SCLK.
As a result, test data SOUT are serially outputted (i.e., 0, 1, 2, 3, 4 . . . ) through an output unit. At this time, the output unit outputs the input signal received through the input pin I/O_n adjacent to the output unit as 0-th test data SOUT. Furthermore, the output unit outputs the input signals received through the respective input pins as first to n-th test data SOUT according to the order of the input pins adjacent to the output unit.
In such a method, however, the test clock signal having a low frequency is used separately from a normal clock signal, and a time required for serially outputting the output signals additionally occurs. Therefore, it is impossible to perform a high-speed test capable of simultaneously checking all of the signal input paths according to a time flow. Therefore, it was impossible to normally check an issue related to speed, such as a coupling issue or margin issue. However, an actual clock signal at which a processor and a memory operate is faster than the test clock signal, and a new test method is urgently required to guarantee the reliability of continuous signal transmission operations at such a high frequency.
The new test method may include a loopback test method of directly feeding back a transmitted signal to the same path through a bi-directional I/O unit provided between a processor and a memory. However, the loopback test method may be performed only when the bi-directional I/O unit is provided. Therefore, there is a demand for a method for performing a high-speed test for a uni-directional I/O unit.